RAM 7.0 manuals

Ram 7.0 User Manual (16 pages)

Brand: Ram | Category: Audio amplifiers | Size: 0.26 MB |

German

English

French

Table of contents

DQL Series

1

2.4 / 4.0 / 5.5 / 7.0

1

VORSICHT

3

ATTENTION

3

INHALTSVERZEICHNIS

4

TABLE DES

4

MATIÈRES

4

General Information

5

Informations

5

Générales

5

Allgemeine

5

Anweisungen

5

Dual Channel

10

Parallel Inputs

10

Single Channel

10

Protection Systems

12

Systèmes de

12

Protection

12

SSyysstteemm

12

Technical

15

Specifications Spécifications

15

Tecnische

15

Spezifikationen

15

Ram 7.0 Specifications (28 pages)

Brand: Ram | Category: Audio amplifiers | Size: 3.29 MB |

English

Table of contents

RAM-3500-LCD

1

Table of Contents

3

List of Figures

4

List of Tables

5

1.0 Introduction

6

2.0 Mechanical Installation

8

1. Open the front door

9

Introduction

10

Component Function

11

3.2 Dip Switches

12

3.2.2 Configuring Functions

13

Function Switch # Enable

13

Set switch to OFF

13

Set switch to ON

13

4.0 Wiring

14

4.1 RAM-3500-LCD Wiring

15

5.0 Operation

16

LED Indicator and

18

Control Buttons

18

Description

18

5.3.1 Flash Rates

21

6.0 Specifications

22

© MGC 2014

28

Printed in Canada

28

Ram 7.0 User's Guide (118 pages)

Brand: Ram | Category: Audio amplifiers | Size: 3.67 MB |

English

Table of contents

LogiCORE IP Block

1

Memory Generator v6.1

1

Features

2

Overview

3

Applications

3

Supported Devices

3

Memory Types

4

$;,0DVWHU

8

:ULWH&KDQQHOV

8

$;,0DVWHU

8

5HDG&KDQQHOV

8

Product Specification

10

AXI4 Wrap Burst Support

12

X-Ref Target - Figure 14

14

AXI4 Unaligned Transactions

16

Configurable Width and Depth

17

Throughput & Performance

18

Selectable Port Aspect Ratios

18

Optional Output Register

18

Optional Pipeline Stages

19

Simulation Models

19

Memory Type

19

Selectable Memory Algorithm

22

Fixed Primitive Algorithm

23

Selectable Width and Depth

25

X-Ref Target - Figure 26

26

X-Ref Target - Figure 27

26

X-Ref Target - Figure 30

28

Collision Behavior

30

ADDRA = ADDRB = 0

31

DOUTB is shown for when port

31

Optional Output Registers

32

REGCE pin, the last output

36

EN signal

36

Optional Set/Reset Pins

37

Memory Output Flow Control

37

Disabled ReadReset When

38

Read No Reset

38

When EN=’0’

38

Operation

39

ReadReset Read Reset

39

Asynchronous Reset

41

1111 2222

45

X-Ref Target - Figure 48

48

Signal Lists

56

AXI4-Interface Signals

57

Name Direction Description

58

AXI4-Lite Interface Signals

60

ENA pin available)

67

ENB pin available)

67

Block RAM Usage

73

Examples

77

Output Registers

78

Aspect Ratios

80

Algorithm

81

Low Power Designs

84

Auto Upgrade Feature

86

X-Ref Target - Figure 62

87

Configurations

96

Core Output Registers

97

Port A or Port B

100

Output of Memory Core Enabled

111

References

116

Support

117

Ordering Information

117

Revision History

117

Notice of Disclaimer

118

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